1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage of the transistor, then there is no conductive channel formed and the FET is “off”, i.e., there is no current flow (ignoring undesirable leakage currents which are relatively small). However, when a voltage is applied to the gate electrode that exceeds the threshold voltage (“Vt”) of the device, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. The threshold voltage of transistor devices is a very important characteristic of such devices. There are two types of FETs (i.e., N-channel and P-channel) as defined by the formation of conductive channels of electrons (N-type) and holes (P-type). The conductive channels are electrostatically induced when the gate bias is higher (N-type) or lower (P-type) voltage than the source region. The source and the drain regions are doped N-type and P-type for N-channel and P-channel FETs, respectively. A digital circuit typically includes both N-type and P-type MOSFETs and is generally referred to as Complementary-MOSFET (or CMOS). A typical inverter of logic includes one N-channel and one P-channel MOSFET connected in series.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. The well-known “Moore's law” of scaling guides the semiconductor industry to advance one CMOS technology node by doubling the density of FETs about every two years. More specifically, the channel length of FETs has been significantly decreased, e.g., about a 70% linear scaling at every technology node, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region and the control of the electrical potential of the channel from the gate. In some cases, this decrease in the gate length and the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain (e.g., the threshold voltage (“Vt”) decreases and leakage current increases with smaller channel length). This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called three-dimensional (“3D”) devices, such as an illustrative FinFET device, which is a 3D structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate structure (including a gate dielectric and a gate electrode) encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3D structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, silicon dioxide, etc., that is typically thicker than the gate insulation layer is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a thin channel region (or fin) is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical foot print of the semiconductor device. The potential of the vertical fin (or channel) is controlled by the tri-gate surrounding both sides and the top of the fin, thus the on-off characteristics of the devices is better controlled by the gate voltage than the planar FET and thus greatly reduce the “short-channel-effects.” As with planar FETs, there are N-channel and P-channel FinFETs wherein a conductive channel is electrostatically induced along the sidewalls and top surface of the fin when the FinFET device is turned “on.”
The sophistication and complexity of integrated circuit products has increased greatly in recent years. Many integrated circuit products are based upon the concept of system-on-chip (SOC) integrated circuits wherein a single chip may contain different circuit blocks that are adapted to perform different tasks. Customers continue to demand high-performance integrated circuit products that exhibit greater performance and greater flexibility in terms of product design and capabilities. Thus, there is a need for FinFET devices, both P-type and N-type devices (in CMOS circuits), that have variations in the threshold voltages (“Vt”) of such devices, e.g., high, medium and low threshold voltages (for both N-type and P-type FinFETs), to give device designers greater flexibility and options in designing complex integrated circuits. There have been various attempts in the prior art to produce FinFET devices in such a manner that the Vt of the devices may be varied or tuned by various process steps. One prior art technique involved attempting to tune the threshold voltage of such devices by selectively controlling the amount of dopant in the channel region, i.e., by performing various ion implantation processes whereby varying doses of dopant were implanted in selective areas. Another prior art technique involves producing a device with multiple fins wherein the fins have different fin widths, wherein the wider fins can include more dopants in the channel region which increases the Vt of the device for the same ion implantation step. Other prior art techniques involve the selective change of the work-function of a metal gate stack by implanting arsenic into the metal gate stack, adjusting the thickness of metal layers, adding capping layers to gates, etc. However, these processes have not been readily adopted because of a variety of reasons. For example, the aforementioned selective ion implantation processes may tend to damage the metal gate stacks, the gate dielectric and/or the channel region. Some of the other prior art attempts tend to greatly increase processing complexity by extra process steps of masking, etching, thin film deposition, chemical mechanical polishing (CMP), annealing, etc. Additionally, some of the prior art techniques that were based on varying ion implantation processes and/or fin width adjustments resulted in devices having very large variations in threshold voltage (Vt) when the devices had very small gate lengths and narrow gate lengths.
The present disclosure is directed to various methods of forming FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.